1. Technical Field
This invention relates in general to semiconductor devices and, more specifically, to receivers and other input buffers having differential inputs and outputs, low skew, and a disable feature. Such receivers are particularly useful in synchronous semiconductor memories.
2. Related Art
Most Dynamic Random Access Memories (DRAMs) have an asynchronous timing relationship with other electronic devices they interact with. In recent years, however, synchronous DRAMs have become popular because they provide faster memory access than asynchronous DRAMs.
One type of synchronous DRAM, known as a "SynchLink" DRAM (SLDRAM), is shown in FIG. 1. The non-prior art SLDRAM 10 receives command packets containing command and address signals from a memory controller 12 via a 10-bit-wide command link, and these command packets are latched into the SLDRAM 10 in response to a differential command clock (CCLK, CCLK*). Similarly, the SLDRAM 10 and memory controller 12 share write and read data via a bidirectional, 16-bit-wide datalink, and this data is latched into or out of the SLDRAM 10 in response to one of two differential data clocks (DCLK0, DCLK0*) and (CCLK1, DCLK1*). The particular data clock (DCLK0, DCLK0*) or (DCLK1, DCLK1*) in use at any given time is determined by command signals from the memory controller 12.
Within the SLDRAM 10, a delay locked-loop (DLL) 14 generates a delayed command clock CCLKD in response to the command clock (CCLK, CCLK*) and control signals 16 received from control logic 18. The delayed command clock CCLKD, in turn, causes a command latch 20 to latch in a command packet from the command link. The command packet is then made available to the control logic 18, which responds by directing read/write (R/W) circuitry 22 to access a memory array 24 of the SLDRAM 10.
Also, a delay-circuit 26 generates a delayed write data clock DCLKW and a delayed read data clock DCLKR in response to control signals 28 from the control logic 18 and the data clock (DCLK0, DCLK0*) or DCLK1, DCLK1*) selected by the memory controller 12. In a write operation, the delayed write data clock DCLKW causes a data latch 30 to latch in write data from the datalink, which is then made available to the R/W circuitry 22 for storage in the memory array 24. In a read operation, the delayed read data clock DCLKR causes the data latch 30 to latch in read data from the R/W circuitry 22 and memory array 24, which is then transferred over the datalink to the memory controller 12.
Each of the differential clocks (CCLK, CCLK*), (DCLK0, DCLK0*) and (DCLK1, DCLK1*) is typically buffered by a differential receiver within the SLDRAM 10. For example, as shown in FIG. 2, the delay circuit 26 generally includes a differential receiver 34 that buffers the differential data clock (DCLK0, DCLK0*) and outputs a corresponding differential data clock (DCLK0OUT, DCLK0OUT*) suitable for internal use by the SLDRAM 10 (FIG. 1).
Proper operation of the SLDRAM 10 (FIG. 1) generally requires that the differential receiver 34 exhibit low timing skew. Also, because the data clock (DCLK0, DCLK0*) is only operative intermittently (recall that the memory controller 12 (FIG. 1) periodically selects one or the other of the data clocks (DCLK0, DCLK0*) and (DCLK1, DCLK1*) for current use), it is desirable for the differential receiver 34 to have a disable feature which causes it to output a "0" state on its outputs DCLK0UT and DCLK0UT* when the other data clock (DCLK1, DCLK1*) (FIG. 1) is the operative data clock. Of course, the differential receiver 34 does not require a disable feature if it is used to buffer the command clock (CCLK, CCLK*) (FIG. 1) rather than the data clock (DCLK0, DCLK0*).
Various input buffers, receivers, and low skew circuit architectures are known in the art, including, for example, those described in U.S. Pat. Nos. 4,958,088, 5,164,619, 5,278,460, 5,311,081, 5,361,002, 5,432,823, 5,465,060, 5,539,333, 5,570,042, 5,578,941, 5,625,805, and 5,666,067. But none of these satisfy the requirements of a receiver for the SLDRAM described above.
Therefore, there is a need in the art for a receiver having differential inputs and outputs that exhibits low timing skew and, preferably, has a disable feature for use with intermittent data clocks. Such a receiver would be particularly useful with the SLDRAM described above and with other SDRAMs.